mmCM0_CM_DGAM_RAMA_END_CNTL2_R 3706 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x0cd0
mmCM0_CM_DGAM_RAMA_END_CNTL2_R 4460 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x0d46
mmCM0_CM_DGAM_RAMA_END_CNTL2_R 3522 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x0d46