mmCM0_CM_DGAM_RAMA_END_CNTL2_B 3698 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x0ccc
mmCM0_CM_DGAM_RAMA_END_CNTL2_B 4452 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x0d42
mmCM0_CM_DGAM_RAMA_END_CNTL2_B 3514 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x0d42