mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 3705 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX                                                        2
mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 4459 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX                                                        2
mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 3521 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX                                                        2