mmCM0_CM_DGAM_RAMA_END_CNTL1_R 3704 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x0ccf
mmCM0_CM_DGAM_RAMA_END_CNTL1_R 4458 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x0d45
mmCM0_CM_DGAM_RAMA_END_CNTL1_R 3520 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x0d45