mmCM0_CM_DGAM_RAMA_END_CNTL1_G 3700 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x0ccd
mmCM0_CM_DGAM_RAMA_END_CNTL1_G 4454 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x0d43
mmCM0_CM_DGAM_RAMA_END_CNTL1_G 3516 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x0d43