mmCM0_CM_DGAM_RAMA_END_CNTL1_B 3696 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x0ccb
mmCM0_CM_DGAM_RAMA_END_CNTL1_B 4450 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x0d41
mmCM0_CM_DGAM_RAMA_END_CNTL1_B 3512 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x0d41