mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 3682 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x0cc4
mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 4436 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x0d3a
mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 3498 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x0d3a