mmCM0_CM_CONTROL_BASE_IDX 3583 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_CONTROL_BASE_IDX                                                                      2
mmCM0_CM_CONTROL_BASE_IDX 4373 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_CONTROL_BASE_IDX                                                                      2
mmCM0_CM_CONTROL_BASE_IDX 3435 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_CONTROL_BASE_IDX                                                                      2