mmCM0_CM_CONTROL 3582 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM0_CM_CONTROL                                                                               0x0c92
mmCM0_CM_CONTROL 4372 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_CONTROL                                                                               0x0d1a
mmCM0_CM_CONTROL 3434 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_CONTROL                                                                               0x0d1a