mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 4546 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0d71
mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 3608 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0d71