mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 4542 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0d6f
mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 3604 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0d6f