mmCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 6321 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX                                                            1
mmCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 6565 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX                                                            1
mmCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 6577 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX                                                            1