mmCGTS_CU3_SP0_CTRL_REG_BASE_IDX 6317 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCGTS_CU3_SP0_CTRL_REG_BASE_IDX                                                               1
mmCGTS_CU3_SP0_CTRL_REG_BASE_IDX 6561 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCGTS_CU3_SP0_CTRL_REG_BASE_IDX                                                               1
mmCGTS_CU3_SP0_CTRL_REG_BASE_IDX 6573 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCGTS_CU3_SP0_CTRL_REG_BASE_IDX                                                               1