mmCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX 6301 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX                                                            1
mmCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX 6545 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX                                                            1
mmCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX 6557 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX                                                            1