mmCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX 6391 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX                                                           1
mmCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX 6635 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX                                                           1
mmCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX 6647 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX                                                           1