mmCGTS_CU0_SP0_CTRL_REG_BASE_IDX 6287 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCGTS_CU0_SP0_CTRL_REG_BASE_IDX                                                               1
mmCGTS_CU0_SP0_CTRL_REG_BASE_IDX 6531 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCGTS_CU0_SP0_CTRL_REG_BASE_IDX                                                               1
mmCGTS_CU0_SP0_CTRL_REG_BASE_IDX 6543 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCGTS_CU0_SP0_CTRL_REG_BASE_IDX                                                               1