mmCC_UVD_HARVESTING_BASE_IDX   35 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h #define mmCC_UVD_HARVESTING_BASE_IDX                                                                   1
mmCC_UVD_HARVESTING_BASE_IDX  391 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h #define mmCC_UVD_HARVESTING_BASE_IDX                                                                   1
mmCC_UVD_HARVESTING_BASE_IDX  394 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h #define mmCC_UVD_HARVESTING_BASE_IDX                                                                   1