mmCB_HW_CONTROL_1_BASE_IDX 2959 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCB_HW_CONTROL_1_BASE_IDX                                                                     0
mmCB_HW_CONTROL_1_BASE_IDX 1041 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCB_HW_CONTROL_1_BASE_IDX                                                                     0
mmCB_HW_CONTROL_1_BASE_IDX 1011 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCB_HW_CONTROL_1_BASE_IDX                                                                     0
mmCB_HW_CONTROL_1_BASE_IDX  977 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCB_HW_CONTROL_1_BASE_IDX                                                                     0