mmBL_PWM_PERIOD_CNTL_BASE_IDX 1865 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmBL_PWM_PERIOD_CNTL_BASE_IDX                                                                  2
mmBL_PWM_PERIOD_CNTL_BASE_IDX 10408 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmBL_PWM_PERIOD_CNTL_BASE_IDX                                                                  2
mmBL_PWM_PERIOD_CNTL_BASE_IDX 12779 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmBL_PWM_PERIOD_CNTL_BASE_IDX                                                                  2
mmBL_PWM_PERIOD_CNTL_BASE_IDX 11353 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmBL_PWM_PERIOD_CNTL_BASE_IDX                                                                  2