mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 1867 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX                                                                2
mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 10410 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX                                                                2
mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 12781 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX                                                                2
mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 11355 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX                                                                2