mmBL_PWM_CNTL2_BASE_IDX 1863 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmBL_PWM_CNTL2_BASE_IDX                                                                        2
mmBL_PWM_CNTL2_BASE_IDX 10406 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmBL_PWM_CNTL2_BASE_IDX                                                                        2
mmBL_PWM_CNTL2_BASE_IDX 12777 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmBL_PWM_CNTL2_BASE_IDX                                                                        2
mmBL_PWM_CNTL2_BASE_IDX 11351 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmBL_PWM_CNTL2_BASE_IDX                                                                        2