mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 1313 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                          2
mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 8173 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                          2
mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 7143 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                          2