mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX 1319 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                               2
mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX 8179 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                               2
mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX 7149 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                               2