mmBL1_PWM_BL_UPDATE_SAMPLE_RATE   58 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                         0x162f
mmBL1_PWM_BL_UPDATE_SAMPLE_RATE   54 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                         0x162f
mmBL1_PWM_BL_UPDATE_SAMPLE_RATE   61 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                         0x162f
mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 1316 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                                                0x03e5
mmBL1_PWM_BL_UPDATE_SAMPLE_RATE  468 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162F
mmBL1_PWM_BL_UPDATE_SAMPLE_RATE   58 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                         0x162f
mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 8176 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                                                0x17b7
mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 7146 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                                                0x17b7