mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 1483 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 1805 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 1449 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 1411 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2