mmAZALIA_RIRB_AND_DP_CONTROL 6678 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h #define mmAZALIA_RIRB_AND_DP_CONTROL                                            0x17eb
mmAZALIA_RIRB_AND_DP_CONTROL 6840 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmAZALIA_RIRB_AND_DP_CONTROL                                            0x17eb
mmAZALIA_RIRB_AND_DP_CONTROL 8185 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmAZALIA_RIRB_AND_DP_CONTROL                                            0x17eb
mmAZALIA_RIRB_AND_DP_CONTROL 1482 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmAZALIA_RIRB_AND_DP_CONTROL                                                                   0x04c3
mmAZALIA_RIRB_AND_DP_CONTROL  435 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h #define mmAZALIA_RIRB_AND_DP_CONTROL 0x17C0
mmAZALIA_RIRB_AND_DP_CONTROL 5437 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h #define mmAZALIA_RIRB_AND_DP_CONTROL                                            0x17c0
mmAZALIA_RIRB_AND_DP_CONTROL 1804 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
mmAZALIA_RIRB_AND_DP_CONTROL 1448 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
mmAZALIA_RIRB_AND_DP_CONTROL 1410 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9