mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 1495 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 1817 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 1461 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 1423 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2