mmAZALIA_MEM_PWR_STATUS_BASE_IDX 1541 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
mmAZALIA_MEM_PWR_STATUS_BASE_IDX 1863 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
mmAZALIA_MEM_PWR_STATUS_BASE_IDX 1507 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
mmAZALIA_MEM_PWR_STATUS_BASE_IDX 1469 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2