mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 1509 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 1831 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 1475 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 1437 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2