mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 1547 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 1873 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 1517 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 1479 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2