mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 6508 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                 0x182a
mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 6670 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                 0x182a
mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 8015 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                 0x182a
mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 1546 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0502
mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL  417 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x17D5
mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 5276 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                 0x17d5
mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 1872 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 1516 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 1478 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408