mmAZALIA_CRC1_CONTROL0_BASE_IDX 1529 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
mmAZALIA_CRC1_CONTROL0_BASE_IDX 1851 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
mmAZALIA_CRC1_CONTROL0_BASE_IDX 1495 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
mmAZALIA_CRC1_CONTROL0_BASE_IDX 1457 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2