mmAZALIA_CRC0_CONTROL1_BASE_IDX 1521 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
mmAZALIA_CRC0_CONTROL1_BASE_IDX 1843 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
mmAZALIA_CRC0_CONTROL1_BASE_IDX 1487 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
mmAZALIA_CRC0_CONTROL1_BASE_IDX 1449 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2