ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 6622 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                       0x377c
ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 6784 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                       0x377c
ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 8129 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                       0x377c
ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 17976 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
ixAZALIA_F2_CODEC_PIN_CONTROL_HBR  149 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377C
ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 5388 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                       0x377c
ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 12976 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 16396 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 12723 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c