cfgPSWUSCFG0_MEM_BASE_LIMIT   43 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h #define cfgPSWUSCFG0_MEM_BASE_LIMIT                                                                     0x0020
cfgPSWUSCFG0_MEM_BASE_LIMIT   43 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h #define cfgPSWUSCFG0_MEM_BASE_LIMIT                                                                     0x0020