cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP 1535 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_offset.h #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP                                                       0x0444
cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP  815 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP                                                       0x0444