cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 1194 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_offset.h #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL                                               0x045c
cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL  473 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL                                               0x045c