bADClkPhase       365 drivers/staging/rtl8192e/rtl8192e/r8192E_phyreg.h #define bADClkPhase			0x4000000
bADClkPhase       524 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h #define	bADClkPhase		0x4000000
bADClkPhase       620 drivers/staging/rtl8723bs/include/Hal8192CPhyReg.h #define		bADClkPhase				0x4000000	/*  Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */