BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 105868 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                      0x000001C0L
BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 33400 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                      0x000001C0L