VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 6690 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 6505 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 6328 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 11838 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 5285 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000 VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 5927 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000 VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 6529 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000 VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 6407 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000 VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 7763 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 7426 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 7853 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L