VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 6728 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                        0x0F000000L
VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 6543 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                        0x0F000000L
VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 6366 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                        0x0F000000L
VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 11826 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0f000000L
VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 5323 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000
VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 5965 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000
VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 6567 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000
VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 6445 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000
VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 7801 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                        0x0F000000L
VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 7464 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                        0x0F000000L
VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 7891 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                        0x0F000000L