VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 6716 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                        0x15
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 6531 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                        0x15
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 6354 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                        0x15
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 11821 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x00000015
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 5322 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 5964 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 6566 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 6444 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 7789 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                        0x15
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 7452 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                        0x15
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 7879 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                        0x15