VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 6727 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                          0x00E00000L
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 6542 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                          0x00E00000L
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 6365 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                          0x00E00000L
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 11820 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00e00000L
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 5321 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 5963 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 6565 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 6443 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 7800 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                          0x00E00000L
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 7463 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                          0x00E00000L
VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 7890 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                          0x00E00000L