VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 6702 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                          0x1c
VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 6517 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                          0x1c
VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 6340 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                          0x1c
VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 5310 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 5952 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 6554 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 6432 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 7775 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                          0x1c
VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 7438 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                          0x1c
VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 7865 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                          0x1c