BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 92469 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h #define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 24527 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h #define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL