VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 12065 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0x0000000c
VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 17932 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc
VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 20190 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc
VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 20792 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc