VGT_DEBUG_REG32__tess_topology_p5_q_MASK 12064 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x00003000L
VGT_DEBUG_REG32__tess_topology_p5_q_MASK 17931 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000
VGT_DEBUG_REG32__tess_topology_p5_q_MASK 20189 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000
VGT_DEBUG_REG32__tess_topology_p5_q_MASK 20791 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000