VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 11396 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18
VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 11208 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18
VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 12462 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18
VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 2065 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT                                                        0x18
VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 9472 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x00000018
VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 11012 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18
VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 1615 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT                                                        0x18
VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT  115 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT                                                        0x18
VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT  116 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT                                                        0x18