UVH_GR1_TLB_INT1_CONFIG_M_MASK  377 arch/ia64/include/asm/uv/uv_mmrs.h #define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
UVH_GR1_TLB_INT1_CONFIG_M_MASK 1327 arch/x86/include/asm/uv/uv_mmrs.h #define UVH_GR1_TLB_INT1_CONFIG_M_MASK			0x0000000000010000UL