UVH_GR1_TLB_INT1_CONFIG_DM_MASK 367 arch/ia64/include/asm/uv/uv_mmrs.h #define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL UVH_GR1_TLB_INT1_CONFIG_DM_MASK 1322 arch/x86/include/asm/uv/uv_mmrs.h #define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL